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Intel Rocket Lake-S to use hybrid chiplet architecture for 25% performance boost

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Intel’s new Xe graphics architecture may soon arrive as an integrated desktop graphics solution for its upcoming Rocket Lake-S processor. With Rocket Lake-S rumored to launch later this year, barring any development or production delays caused by current uncertainties surrounding the global COVID-19 pandemic, we could see Intel’s integrated Gen 12 graphics, which are based on Xe, paired with this new processor.

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While Intel has not confirmed Rocket Lake-S, the processor series was previously mentioned in a leaked processor road map. It’s believed that Intel will utilize a hybrid chiplets approach, combining a 14nm process for the processor with a 10nm process for its Gen12 graphics based on the Xe architecture.

At the time, it was speculated that Rocket Lake-S CPU could top out with up to 10 cores, but more recent leaks suggest that Intel may cap it at eight cores. The hybrid chiplets architecture would allow Intel to — as stated on a leaked slide posted by VideoCardz — increase performance with the processor core architecture.

Intel Rocket Lake-S leak
Credit: Videocardz Image used with permission by copyright holder

According to Tom’s Hardware, Intel will likely use a backported version of Tiger Lake’s Willow Cove microarchitecture. Tiger Lake is slated to debut this year as Intel’s silicon solution for mobile, succeeding the 10th-gen Ice Lake platform.

If this is accurate, it could mean a further boost in instructions per clock (IPC) by as much as 5% to 10% compared to Intel’s 10th Gen Ice Lake platform based on the Sunny Cove microarchitecture. Given that Ice Lake already delivered an 18% IPC improvement over Skylake, Tom’s Hardware speculated that Rocket Lake-S could deliver a 25% boost in IPC performance compared to the aging Skylake platform.

The leaked slides, which VideoCardz claimed were obtained from anonymous Intel sources, did not provide information on clock speeds. If the leak is accurate in stating Intel’s reliance on a 14nm process — rather than 10nm — this could be a positive thing for those looking for faster clock speeds. Intel had stated in the past that 14nm was more ideal for clock speeds than its 10nm process.

The 14nm desktop processor will come with some big upgrades as well, including one to PCIe 4.0 (which gained support from rival AMD last year with the company’s Ryzen silicon), Direct Media Interface (DMI) 3.0 x8 support, Thunderbolt 4 and USB 3.2 20G, and HDMI 2.0b and DisplayPort 1.4a support. The PCIe 4.0 support is notable in that it will allow faster data transfers, as well as provide four additional PCIe 4.0 lanes for storage, allowing the GPU and NVMe storage to hook up directly to the CPU instead of the platform controller hub.

Intel will rely on a new Gen12 graphics with the launch of Rocket Lake, which is said to be based on the new Xe architecture that it is using on its discrete DG1 GPU. The new graphics architecture is said to support AV1 encode and decode, which will offload the burden of this task from the CPU to the GPU. It’s still unclear if the integrated graphics will be a backported version of the 14nm Tiger Lake version from earlier rumors, or if it will be an entirely different chiplet.

Stock photo of Intel 9th gen core processor
Intel Newsroom/Intel Corporation

For peripherals, Intel will support the new Intel Thunderbolt 4 standard, which still relies on PCIe 3.0 and not the new PCIe 4.0 standard. Intel shows that Thunderbolt 4.0 devices, along with wireless networking cards, will connect to the Intel 500 series chipset, rather than directly to the CPU. This means that transfer speeds will still be capped at 40 Gbps, the same as on Thunderbolt 3. Notably, Thunderbolt 4 is described to be USB 4.0 compliant.

Other new features include new overclocking capabilities and faster DDR4 speeds, as well as USB audio offload. The leaked slide states that LPC, eMMC, SD 3.0, and SDXC support will be removed from this chip. Intel is also removing support for Intel Software Guard Extensions from the platform.

Chuong Nguyen
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